The present invention relates to a method for correcting exposure patterns to correct for the proximity effect in exposure in a lithography process of semiconductor device manufacture, as well as to an exposing method, a photomask, a semiconductor device, an exposure data correction apparatus, an exposure apparatus, and a semiconductor device manufacturing apparatus using the above correction method.
At present, device structures are increasingly miniaturized with increases in the degree of integration and functionality and, as a result, pattern deformation due to the proximity effect in exposure is problematic in lithography steps of device manufacturing processes. For example, where light is used as exposure energy beams, if the device design rule is at such a level that the line width is close to the exposure wavelength, the interference effect of exposure light becomes remarkable, resulting in differences between design patterns and transferred resist patterns.
The proximity effect takes form, for instance, as dimensional differences between isolated patterns and line/space patterns and contraction at pattern end portions. In particular, the proximity effect tends to occur more likely in repetitive memory cells which are required to have a high degree of integration. In devices of the 0.35-.mu.m generation onward, the proximity effect takes form as width variations of isolated lines and contraction of line end portions not only in repetitive memory cell regions as mentioned above but also peripheral circuit regions of memories and one-chip random circuit regions of ASIC-type devices, which causes deterioration of the line width controllability in devices and decreases of alignment margins in processes. As a result, variations of the device characteristics increase, ending up with a reduction in chip yield. In this manner, the proximity effect very adversely affects the efficiency of manufacture.
The above-mentioned pattern distortion due to the proximity effect is now prevented in the following manner. Where light is used as the energy beams, the shapes of photomask patterns, i.e., the shapes of drawing patterns for forming the photomask, are corrected. Where an electron beam is used as the energy beam, the shapes of drawing patterns and the irradiation amount (exposure amount) of the electron beam are corrected. For example, the above correction is performed in converting layout-designed exposure patterns (hereinafter referred to as "design patterns" ) into mask patterns through pattern calculation processing.
Further, for memory cells of the 0.35-.mu.m generation onward, automatic optical proximity effect correction (OPC) systems have been developed that are based on light intensity simulation. The processing time of the proximity effect correction by such automatic OPC systems is tens of seconds in the case of correction for a several-micrometer-square cell. However, if such a system itself is used for proximity effect correction of a chip-scale ransom pattern, it will take hundreds of days.
In view of the above, there have been proposed, as methods for enabling chip-level proximity effect correction, rule-based methods that perform correction processing only on certain limited pattern shapes according to preset rules.
However, the above correction methods have the following problems because they correct design patterns.
That is, having a hierarchical structure, design patterns are complex in data structure. Further, to correct design patterns, they need to be subjected to pattern calculation processing in advance. To this end, pattern data needs to be developed. Therefore, not only does the data size become enormous but also the process itself becomes complex. Thus, even the rule-based methods cannot shorten the entire processing time to a practical level.
From the viewpoint of processing time, conventional manufacturing processes of a semiconductor device employ the above correction process that provides partial design patterns. Therefore, when design patterns of one chip are completed, the design patterns have already been corrected. Circuit simulation is performed on the corrected design patterns. Since the corrected design patterns are different from patterns to be formed on a wafer, results of the circuit simulation should be low in reliability.